The present invention relates to a scanning line driving circuit, a display device, and a portable electronic apparatus, and particularly, to a scanning line driving circuit for a display device using an active matrix substrate.
In recent years, notebook personal computers and monitors equipped with liquid crystal display devices using active elements, such as thin film transistors (TFTs), have been rapidly spread. Particularly, a much attention has been paid to a poly silicon TFT in which polysilicon is used for an active layer thereof since driving circuits to be mounted on a substrate using the high movability of the polysilicon TFT.
A general liquid crystal display device using a nematic liquid crystal material requires alternating current driving in which the polarity of a voltage applied to liquid crystal is reversed at a predetermined time in order to secure the reliability of the device. Since the difference between the voltages applied to the liquid crystal at the time of white display and at the time of black display is in the range of 3 to 5 V, in order to perform the alternating current driving, signals having a voltage amplitude of 6 to 10 V should be input to pixel electrodes on an active matrix substrate. Further, in order to obtain a sufficient switching characteristic, it is necessary to apply a voltage greater than that of the signal input to the pixel electrodes by 2 to 5 V to scanning lines connected to gates of pixel switching TFTs. Finally, a scanning line driving circuit of the liquid crystal display device needs to output a signal voltage of about 8 to 15 V. The voltage tends to increase with an increase in the side and precision of the liquid crystal display device. In addition, when the scanning line driving circuit is mounted on a glass substrate, it is general to drive the scanning line driving circuit at a voltage of 10 to 15 V.
Further, a self-emitting display device using organic EL (OLE) elements is currently being developed as a next-generation display device. However, a polysilicon TFT active matrix capable of flowing a large amount of current is generally used for driving the organic EL elements. In this case, a voltage of 5 to 20 is also needed to drive the organic EL elements, and thus it is necessary to apply, to the scanning lines, a voltage equal to or greater than that used for the liquid crystal display device.
However, a timing signal or a clock signal required to driving the scanning line driving circuit is generally input from an external IC. Therefore, in order for an IC to output a signal having a voltage amplitude greater than 5 V, it is necessary to manufacture an IC having high voltage resistance using a special manufacturing process, which causes an increase in costs.
In order to solve the above-mentioned problems, a circuit configuration is effective in which a level shifter is incorporated into a scanning line driving circuit mounted on a glass substrate and the voltage of a signal having a voltage amplitude of 3 to 5 V input from an IC is raised to a voltage amplitude of 8 to 15 V. For example, Patent Document 1 discloses a method in which the voltage of a signal input from an IC circuit is raised and the voltage-raised signal is then input to a shift register.
However, in the case of a polysilicon TFT, particularly, a so-called low-temperature process polysilicon (LTPS) TFT obtained by forming polysilicon on a no-alkali glass substrate at a temperature of less than 600° C., a gate insulating film is generally formed by a chemical vacuum deposition (CVD) method, which has voltage resistance and defect density lower than those of a gate insulating film formed by a thermal oxidation method generally used for forming a transistor on a monocrystalline silicon wafer. Therefore, it is not preferable to apply a high voltage to the main body of the driving circuit from the viewpoint of reliability and yield.
Meanwhile, with a rapid increase in the performance of a polysilicon TFT in recent years, a logical circuit system including a shift register provided in the scanning line driving circuit can driven at a voltage of 3 to 5 V. Therefore, for example, Patent Document 2 discloses the following configuration: a logical circuit, such as a shift register, is driven at a relatively low voltage (which is referred to as a logical circuit-based power supply voltage); the voltage of a signal output from the logical circuit is raised to a relatively high voltage (which is referred to as a driving circuit-based power supply voltage), and then the signal having a high voltage is input to a scanning line through a buffer circuit. Thus, this configuration has been widely used in recent years since power consumption decreases and reliability increases.
FIG. 10 shows the structure of a conventional scanning line driving circuit. Here, it is considered a scanning line driving circuit for driving a liquid crystal display device having 480 scanning lines. A shift register circuit (350) is mounted in the scanning line driving circuit, and a CLK signal terminal (601), a CLKX signal terminal (602), and an XST signal terminal (603) are connected to the scanning line driving circuit. The shift register has a total of 481 output terminals (504-1 to 504-481) composed of the last terminal and 480 stages, each stage comprising a first clocked inverter (351-n), a second clocked inverter (352-n), and a first inverter (353-n).
In the shift register circuit (350), an n-th (=1 to 480) output terminal (504-n) and an (n+1)-th output terminal (504-n+1) are connected to input terminals of an NAND circuit (505-n), respectively. Here, the first and second clocked inverters (351-n and 352-n), the first inverter (353-n), the NAND circuit (505-n) are connected to power supply terminals having potentials of VD and VS (VD>VS), respectively, and the potential of a signal output from the NAND circuit (505-n) has an amplitude of VD−VS.
An output terminal of the NAND circuit (505-n) is connected to a level shifter (506-n), and the potential of the signal having the amplitude of VD−VS is amplified to a potential of VH−VL. Here, the relationship VH>VD>VS>VL is established. The signal having the potential amplified by the level shifter circuit (506-n) is input to a scanning line through a second inverter (507-n), a third inverter (508-n), and a fourth inverter (509-n). Here, the second to fourth inverters (507-n to 509-n) are respectively composed of buffer circuits for enhancing a driving performance and are respectively connected to a potential VH and a potential VL, both serving as power supplies.
FIG. 12 shows the structure of the level shifter circuit (506-n). The level shifter circuit comprises a separating unit (550) for dividing a signal into a positive polarity and a negative polarity and for outputting them, a High-level amplifying unit (551) for amplifying a signal level of VD−VS to a signal potential of VH−VS, and a Low-level amplifying unit (552) for amplifying a signal potential of VH−VS to a signal potential of VH−VL. The structures of the High-level amplifying unit (551) and the Low-level amplifying unit (552) are known as a so-called flip-flop-type level shifter and are generally used for the scanning line driving circuit since their normal power consumption is small at the time of non-operation. Of course, a structure in which the positions of the High-level amplifying unit (551) and the Low-level amplifying unit (552) are changed to each other can be used. In addition, a structure in which the High-level amplifying unit (551) or the Low-level amplifying unit (552) is absent can be used. However, in this case, when the difference between VH−VL and VD−VS is extremely large, the level shifter is unavailable. Thus, it is necessary to take such a two-stage structure in order to drive a logical circuit at a low voltage.
This structure makes it possible to reduce the driving voltage (VD−VS) of a logic circuit composed of the shift register (305) and the NAND circuit (505-n) in the range where the performance of the polysilicon TFT does not deteriorate, and to secure the necessary driving voltage (VH−VL) of the driving circuit of the buffer unit composed of the second to fourth inverters (507-n to 509-n). Therefore, it is possible to realize a high-quality image, high reliability, and low power consumption.
[Patent Document 1] Japanese Unexamined Patent Application Publication No. 2000-163003
[Patent Document 2] Japanese Unexamined Patent Application Publication No. 2001-265297